Lithographic projection apparatus (tools) can be used, for example, in the manufacture of ICs. When using the various tools, a mask can be used that contains a circuit pattern corresponding to an individual layer of the IC, and this pattern, usually having many designs, can be imaged onto a target portion (e.g., comprising one or more dies) on a substrate, such as a silicon or other wafer comprising a semiconductor surface, that has been coated with a layer of radiation-sensitive material, such as a resist. In general, a single wafer may contain a network of adjacent target portions that can be successively irradiated using a projection system of the tool, one at a time.
One of the goals in IC fabrication is to faithfully reproduce the original IC design on the wafer using the mask. Another goal is to use as much of the wafer area as possible. As the size of an IC is reduced and its density increases, however, the critical dimension (CD) of its corresponding mask approaches the resolution limit of the optical exposure tool. The resolution for an exposure tool can be defined as the minimum feature sizes that the exposure tool can repeatedly expose on the wafer. The resolution value of exposure tools often constrains the CD for many advanced IC designs.
A particularly important fabrication process employed in IC fabrication that includes MOS transistors is the gate electrode (hereafter the “gate”) etch process, such as a polysilicon gate etch process, which is commonly utilized for forming MOS transistors. The gate etch process is important in terms of device operation and CDs. Better or tighter control of the gate etch process results in benefits including better device characteristics, improved device performance, and/or improved device yield. Collectively these benefits improve device yield and/or produce devices with additional intrinsic value (e.g., better performance, lower heat dissipation, lowered leakage current). Thus, a stable, accurate and precise gate etch process for ICs MOS transistors is important.
Gate CD control is becoming more critical and more difficult to achieve node on node. Attention is focused on controlling the CD for gate. For example, polysilicon gate pitch restrictions and dummy features at the ends of gate arrays have been used to improve gate CD performance vs. lithography process variation.